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Digital ASIC & FPGA Design
Digital hardware designed and synthesized in Verilog through an ASIC/FPGA flow, with architectural optimization for performance, area, and power.
Overview
This ECE 564 coursework develops complex digital hardware in synthesizable Verilog through an ASIC and FPGA development flow. Work includes digital architectures, finite-state machines, datapath design, clock-domain crossing, and verification.
Technical
I synthesize RTL with Synopsys Design Compiler, analyze timing and critical paths, and refine the hardware architecture for performance, area, and power. Verification and static timing analysis connect functional behavior to the constraints and tradeoffs of a physical implementation flow.
Tools
ASIC design, FPGA, Verilog, RTL design, logic synthesis, static timing analysis, Synopsys Design Compiler, and digital design.