coursework / completed
Cache & Memory Hierarchy Architecture Simulator
A configurable cache and memory hierarchy simulator for evaluating processor memory-system behavior and architectural tradeoffs.
Overview
For ECE 563, I designed a configurable cache and memory hierarchy simulator to model processor memory-system behavior across architectural configurations. The architecture is the focus; C++ serves as the implementation tool.
Technical
The model implements set associativity, tag, index, and offset addressing, replacement and write policies, dirty and valid state, evictions, and multi-level cache interactions. I evaluated benchmark traces and tradeoffs involving cache size, associativity, latency, hit and miss behavior, and hardware cost.
Tools
Computer architecture, cache architecture, memory systems, microarchitecture, performance analysis, and C++.