Intel
Silicon Engineering Intern
Post-silicon validation and hardware debug for Intel client SoCs, with a focus on power management, platform behavior, and cross-layer root cause analysis.
Overview
I validate pre- and post-silicon Intel Nova Lake and next-generation client SoCs. My work centers on debugging live silicon across clock and PLL, thermal, reset, low-power, and telemetry subsystems, then tracing failures through registers, RTL, firmware, and BIOS to isolate root causes.
Technical
Debug work spans register-level analysis, hardware traces, lab instrumentation, RTL simulation and waveform analysis in Synopsys Verdi, source-level analysis, and platform experimentation. I also build Python automation where it removes repetitive validation work and improves reproducibility.
Impact
I own telemetry validation across more than 500 signals, counters, and operating conditions. I have also built reusable diagnostics and validation workflows that reduce repetitive investigation and make hardware findings easier to reproduce and communicate across engineering teams.
Tools
Synopsys Verdi, hardware traces, register-level debug, RTL simulation, platform validation, lab instrumentation, source-level analysis, and Python.
Day-to-day
A typical debug cycle moves from reproducing a failure on a platform and collecting hardware evidence to testing hypotheses across RTL, firmware, and BIOS, root-causing the behavior, and documenting the result for partner engineering teams.