Experience
Period
May 2026 — Present
Location
Folsom, California

Intel

Silicon Engineering Intern

Working across silicon validation, power-management debug, and engineering automation for client computing platforms.

Overview

My work at Intel sits between silicon, firmware, and software. I help validate power-management behavior on client computing platforms and investigate failures by connecting observations from physical systems with design intent.

Technical

The work includes register-level analysis, RTL simulation, hardware traces, lab measurements, and Python-based automation. Debugging often means narrowing a system-level symptom across silicon, firmware, BIOS, validation methodology, and platform configuration.

Impact

I have built reusable diagnostics and validation workflows that reduce repetitive investigation and make technical findings easier to reproduce and communicate across engineering teams.

Tools

Python, RTL simulation and waveform analysis, register traces, logic analyzers, oscilloscopes, and platform validation tooling.

Day-to-day

A typical cycle moves from reproducing a failure, collecting evidence, forming and testing hypotheses, and documenting the result for engineers working across design, validation, and firmware.